Verified circuit optimisation
Rewrites that reduce depth or two-qubit gate count could be proposed automatically, but would only advance where an independent verifier confirms equivalence within a stated tolerance.
EMERGING DOMAIN · QUANTUM COMPUTATION
Verified transformation
beyond classical software.
RESEARCH DIRECTION · NOT YET DEMONSTRATED
Verinex is being designed as a domain-independent architecture for proposing, testing, rejecting and certifying computational transformations. Quantum circuits and intermediate representations are a prospective future application, subject to specialised verification and experimental validation.
● NOT DEMONSTRATEDNO QUANTUM HARDWARE IN OPERATION|NO QUANTUM RESULTS CLAIMED|ARCHITECTURAL APPLICABILITY · UNDER EVALUATION
01 / ARCHITECTURAL TRANSFER
Why the architecture
may transfer.
The Verinex layers below are defined over artefacts and verdicts, not over any particular execution model. That is the basis for considering quantum artefacts — and it is an argument about structure, not a result. The existing classical semantic verifiers are not sufficient for quantum correctness; new verifiers would have to be built and independently validated before any claim could stand.
- 01Candidate generationProposal of transformations against a stated objective, independent of the artefact's execution model.
- 02FalsificationActive attempts to break a candidate before it is permitted to advance.
- 03Verifier orchestrationStructurally independent verifiers producing signed verdicts on the same artefact.
- 04LineageAppend-only ancestry linking every accepted transformation to the artefacts that justified it.
- 05Evidence captureDeterministic capture of inputs, configuration and execution context for replay.
- 06Sealed certificatesContent-addressed, signed records of what was verified and under which policy.
02 / PROPOSED PIPELINE
A proposed path from
circuit to sealed evidence.
PROPOSED · NOT IMPLEMENTED
- 01INPUTQuantum source or circuit
- 02IRQIR / circuit representation
- 03CANDIDATEVerinex candidate transformation
- 04VERIFY · 1Quantum equivalence verifier
- 05VERIFY · 2Hardware and resource verifier
- 06SEALSealed transformation certificate
CAPTION · THIS IS A PROPOSED ARCHITECTURE, NOT A COMPLETED IMPLEMENTATION. NO STAGE SHOWN HAS BEEN DEMONSTRATED ON QUANTUM ARTEFACTS.
03 / PROSPECTIVE APPLICATIONS
Candidate directions,
none of them results.
Circuit equivalence checking
Equivalence between a candidate circuit and its specification is the central gate. This would require dedicated quantum semantic verifiers; classical test suites are not sufficient.
Hardware-aware transpilation
Mapping to a target topology and native gate set could be treated as a verified transformation rather than an unchecked compiler pass. Under evaluation as an architectural fit.
Reproducible quantum compiler evidence
Compiler stages could emit sealed, replayable evidence so that a produced circuit is defensible after the fact. This would require deterministic capture of toolchain context.
Hybrid classical–quantum workflow governance
Where classical and quantum stages interleave, continuation gates could apply uniformly across both. No such workflow has been implemented or tested.
NO CUSTOMER ADOPTION.
NO PARTNERSHIPS.
NO COMPLETED EXPERIMENTS.
04 / REQUIRED ADAPTATIONS
What quantum
would demand.
Each item below is a condition of correctness that conventional software test suites do not resolve. They are stated as open requirements, not as capabilities.
- Equivalence up to global phase
- Two circuits differing only by a global phase are physically indistinguishable. Verification must treat this as equivalence, not as a difference.
- Probabilistic measurement semantics
- Outcomes are distributions, not values. Correctness must be expressed over distributions and sampling error, not single-run comparison.
- Approximate and tolerance-bounded equivalence
- Exactness is often neither achievable nor required. A verifier must carry an explicit, declared tolerance.
- Entanglement and state-space complexity
- State space grows exponentially with qubit count, bounding what any simulator-backed verifier can decide and for which circuit sizes.
- Hardware topology, native gates and calibration
- A transformation valid in the abstract may be invalid on a given device. Target topology, native gate set and calibration context form part of the claim.
- Simulator and hardware-run provenance
- Whether a verdict came from a simulator or a physical device — and under which parameters — must be recorded as part of the evidence.
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05 / PROPOSED FIRST EXPERIMENT
Simulator-first,
deliberately modest.
The purpose of a first experiment is to test the architecture, not to claim a quantum advantage. Real quantum-hardware access is not required for the initial architectural test.
STATUS · PROPOSED · NOT YET RUN
- 01 · CORPUSSmall QIR or Qiskit-compatible circuits, sized to remain tractable under simulation.
- 02 · CANDIDATESCandidate circuit rewrites proposed against a stated objective.
- 03 · GATEAn independent equivalence gate that must pass before any candidate advances.
- 04 · OBJECTIVESCircuit depth and two-qubit gate count as the measured objectives.
- 05 · REPLAYFresh-harness replay of every accepted transformation, independent of the proposing run.
- 06 · EVIDENCESealed evidence retained for accepted transformations; rejected candidates retained with rationale.
06 / OPEN RESEARCH QUESTION
Can verified quantum transformations compound through reusable lineage while every accepted circuit remains independently equivalent to its specification?
This question is open. It is stated here so that any future result can be measured against it, and so that the absence of a result today is explicit.
07 / QUALIFICATION
Quantum computation is an intended area of investigation, not a demonstrated Verinex capability.
Any future public claim will be placed on the same evidence taxonomy used across the platform.